The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Memory in computing devices may be arranged in a memory hierarchy, which includes memory devices of different speeds, types and sizes. The type, size and proximity of a memory device to a processor affect processing speed of the memory device. Higher levels of the hierarchy generally correspond to higher speed/lower capacity memory devices while lower levels of the hierarchy generally correspond to lower speed/higher capacity devices. For example, cache may be at the highest level, RAM and ROM may be at middle levels, and non-volatile memory such as a hard disk drive may be at the lowest level.
Cache may be used to store copies of highly used data and instructions to improve performance. The cache may be implemented using high speed memory such as static random access memory (SRAM) instead of slower dynamic RAM (DRAM), which may be used for main memory. The cache may be arranged on the same integrated circuit (IC) as the processor and may be referred to as Level 1 (L1) cache.
During operation, the processor executes instructions. More particularly, the processor fetches an instruction having a location identified by a program counter (PC). After fetching the instruction, the processor decodes the instruction, which may include an opcode and an operand. The opcode indicates the operation to be performed while the operand may include information for the operation to be performed. After the fetch and decode steps are performed, the processor executes the instruction. Finally, the processor writes back the results to memory. After completing the instruction, the program counter may be incremented by the length of the instruction word.
Some types of instructions may be called branches or jumps that may be used to directly manipulate the program counter. For example, the branch may be used to facilitate behavior similar to loops, conditional decisions and other program functions. Alternately, the branch may occur as a result of register values, which may represent flags.
The cache may be accessed as a word; each including R instructions, where R is an integer greater than one. Each instruction may include I bits, where I is an integer greater than one. To access the word of instructions, multiple read cycles may be executed. Each read cycle accesses one of the instructions. During the read cycle, memory cells associated with an instruction are accessed by asserting toggling both a row path (a word line) and multiple column paths (bit lines) of the array for the corresponding instruction. The asserting of row and column paths may be accompanied by decoding row and column addresses, generating a word line signal, precharging bit lines, sensing-amplification of stored bit information, and latching data.